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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  xadc_temp_sensor instance_name
(
    .daddr_in(daddr_in[6:0]),         // input [6:0] daddr_in
    .dclk_in(dclk_in),                // input dclk_in
    .den_in(den_in),                  // input den_in
    .di_in(di_in[15:0]),              // input [15:0] di_in
    .dwe_in(dwe_in),                  // input dwe_in                           
    .do_out(do_out[15:0]), //output [15:0] do_out
    .drdy_out(drdy_out), //output drdy_out
    .vccaux_alarm_out(vccaux_alarm_out),     //output vccaux_alarm_out
    .vccint_alarm_out(vccint_alarm_out),     //output vccint_alarm_out
    .user_temp_alarm_out(user_temp_alarm_out), //output user_temp_alarm_out  
    .busy_out(busy_out), //output busy_out
    .channel_out(channel_out[4:0]), //output [4:0] channel_out
    .eoc_out(eoc_out), //output eoc_out
    .eos_out(eos_out), //output eos_out
    .ot_out(ot_out), //output ot_out
    .alarm_out(alarm_out), //output alarm_out
    .vp_in(vp_in),  // input vp_in
    .vn_in(vn_in)   // input vn_in             
      );

// INST_TAG_END ------ End INSTANTIATION Template ---------


